Currently, 100G Single Mode Fiber (“SMF”) and Multi Mode Fiber (“MMF”) standards for Ethernet optical link applications are under development. In general, however, on the transmit side, it is presently contemplated that such high speed transmitters will include a Media Access Control (“MAC”) component that provides data electrically to an optical transmitter. However, since 100 Gigabits per second is simply too fast for present Complementary Metal Oxide Semiconductor (“CMOS”) electrical I/O technology, the 100 Gigabits of electrical data will be provided in several independent electrical lanes.
For instance, perhaps 10 lanes of 10 Gigabits per second of data will be provided from the MAC component to the transmitter. If there were additional overhead used for encoding or error correction, perhaps the data rate for each lane may be increased and/or the number of lanes may be increased. For instance, 66B/64B encoding has been contemplated as being used to encode each lane of 10 Gigabits per second. This would result in each of the 10 lanes of electrical traffic being at an actual data rate of 10.3125 Gigabits per second.
In the transmitter, the 10 lanes of electrical traffic are serialized down to perhaps 4 lanes of optical data, each at a data rate of 25.78125 Gigabits per second, which includes the overhead for 66B/64B encoding. These 4 lanes of optical data may then be multiplexed onto a single fiber using Wavelength Division Multiplexing (“WDM”).
Ethernet data may be transported over longer distances by Dense Wavelength Division Multiplexing (“DWDM”) systems. Currently, standards are under development for defining the use of DWDM technology for transporting 100G Ethernet data. The standard is referred to as OTU4 and encapsulates the Ethernet data in a payload which is then Forward Error Correction (“FEC”) encoded. The resulting fiber data rate is approximately 112 Gigabits per second.
The system (hereinafter called the “100G DWDM OTU4 system”) is contemplated as including two primary components, a Forward Error Correction capable MAC layer (called hereinafter an “OTU4/FEC processor”) and a 100G DWDM capable transponder. In each of the transmit and receive channels, there are 10 lanes of 11 Gigabits per second data that are communicated using the OIF SFI-S interface specification. There is also an eleventh de-skew lane to align all 10 data lanes for serial data transmission.
One of the modulation technologies considered in this 100G DWDM OTU4 system is Dual-Polarization Quadrature Phase-Shift Keying (called “DP-QPSK” for short). The 112 Gigabit per second data stream is contemplated to be divided into four 28 Gb/s data streams, and modulates both I and Q phases of two orthogonally polarized optical carriers having the same wavelength that are transmitted as a single DP-QPSK signal.
On the receive side, an incoming DP-QPSK signal is separated into two orthogonally polarized optical carriers that are processed by a DP-QPSK demodulator to extract the modulation of the I and Q phases of each of the orthogonally polarized optical signals.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced